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| author | William D. Jones <thor0505@comcast.net> | 2020-11-21 11:58:30 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 0364ded385e3ba7817a9e466e165a184292c3ef2 (patch) | |
| tree | fa28a460f6800bfec1bee45238ce98222c64da87 /techlibs | |
| parent | 1b703d3f03eaaf55d2475ee803d546ad4cfc6663 (diff) | |
| download | yosys-0364ded385e3ba7817a9e466e165a184292c3ef2.tar.gz yosys-0364ded385e3ba7817a9e466e165a184292c3ef2.tar.bz2 yosys-0364ded385e3ba7817a9e466e165a184292c3ef2.zip | |
machxo2: Add FACADE_IO simulation model. More comments on models.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 89a66be7f..f09837c13 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -69,10 +69,12 @@ module FACADE_FF #( endgenerate endmodule +/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */ module PFUMX (input ALUT, BLUT, C0, output Z); assign Z = C0 ? ALUT : BLUT; endmodule +/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */ module L6MUX21 (input D0, D1, SD, output Z); assign Z = SD ? D1 : D0; endmodule @@ -141,6 +143,8 @@ module FACADE_SLICE #( end endgenerate + /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F + outputs (in other words, feeds back into FACADE_SLICE). */ wire di0 = (REG0_SD == "1") ? M0 : DI0; wire di1 = (REG0_SD == "1") ? M1 : DI1; @@ -151,3 +155,24 @@ module FACADE_SLICE #( .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET), .REGMODE(REG1_REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1)); endmodule + +module FACADE_IO #( + parameter DIR = "INPUT" +) ( + inout PAD, + input I, EN, + output O +); + generate + if (DIR == "INPUT") begin + assign O = PAD; + end else if (DIR == "OUTPUT") begin + assign PAD = EN ? I : 1'bz; + end else if (DIR == "BIDIR") begin + assign PAD = EN ? I : 1'bz; + assign O = PAD; + end else begin + ERROR_UNKNOWN_IO_MODE error(); + end + endgenerate +endmodule |