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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-12 15:19:41 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-12 15:19:41 -0800 |
| commit | f9aae90e7a9d238f5063d980e2b1e85a94cff4c7 (patch) | |
| tree | 90cdb2422cf1194b6ab72997a82c54e5e0b4818c /techlibs/xilinx | |
| parent | f24de88f385a3eeaadd9b9c8c200a7c338f37448 (diff) | |
| parent | 295e241c074ae275e832fdde9fae6fd897170ac8 (diff) | |
| download | yosys-f9aae90e7a9d238f5063d980e2b1e85a94cff4c7.tar.gz yosys-f9aae90e7a9d238f5063d980e2b1e85a94cff4c7.tar.bz2 yosys-f9aae90e7a9d238f5063d980e2b1e85a94cff4c7.zip | |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 51d2cbbd2..63d00027a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -556,7 +556,6 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); - abc9_opts += " -nomfs"; if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else |