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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-06-26 18:34:34 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-06-26 18:34:34 +0200 |
| commit | ea0b6258ab392b6186ee5d75a75da944b25d0392 (patch) | |
| tree | 17866fa26c6bed6f106709d9a14d4f3ebb14f482 /techlibs/xilinx | |
| parent | 0b7d648c6a71594f8a17e78aef8f62b6f6448390 (diff) | |
| download | yosys-ea0b6258ab392b6186ee5d75a75da944b25d0392.tar.gz yosys-ea0b6258ab392b6186ee5d75a75da944b25d0392.tar.bz2 yosys-ea0b6258ab392b6186ee5d75a75da944b25d0392.zip | |
Simulation model verilog fix
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 50d588a9e..f4598dcf4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -282,7 +282,7 @@ module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); parameter INIT = 32'h0; parameter IS_WCLK_INVERTED = 1'b0; |