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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 12:42:09 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 12:42:09 -0800 |
| commit | d087024cafbd4daf4f4c378b02ba15d6d3cf03d4 (patch) | |
| tree | fb3db49b3417b00ce3438ffd75288820e7674d30 /techlibs/xilinx | |
| parent | 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d (diff) | |
| parent | 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d (diff) | |
| download | yosys-d087024cafbd4daf4f4c378b02ba15d6d3cf03d4.tar.gz yosys-d087024cafbd4daf4f4c378b02ba15d6d3cf03d4.tar.bz2 yosys-d087024cafbd4daf4f4c378b02ba15d6d3cf03d4.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 | ||||
| -rw-r--r-- | techlibs/xilinx/lut_map.v | 8 |
2 files changed, 11 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index fa9be2c33..d863b2ad7 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -126,7 +126,11 @@ endmodule // assign O = IO, IO = T ? 1'bz : I; // endmodule -module INV(output O, input I); +module INV( + (* clkbuf_inv = "I" *) + output O, + input I +); assign O = !I; endmodule diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v index 13d3c3268..62d501632 100644 --- a/techlibs/xilinx/lut_map.v +++ b/techlibs/xilinx/lut_map.v @@ -56,8 +56,12 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin - LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[0])); + if (P_LUT == 2'b01) begin + INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0])); + end else begin + LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0])); + end end else if (WIDTH == 2) begin LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), |