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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-28 12:59:43 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-28 12:59:43 -0800 |
| commit | b1ab7c16c41f0a14b8b14a041367f2259b3c0e37 (patch) | |
| tree | 9788ffffc130438691eb553059a067aab366878e /techlibs/xilinx | |
| parent | a26c52394f193a3f912e0fdbb688c78110a0c974 (diff) | |
| download | yosys-b1ab7c16c41f0a14b8b14a041367f2259b3c0e37.tar.gz yosys-b1ab7c16c41f0a14b8b14a041367f2259b3c0e37.tar.bz2 yosys-b1ab7c16c41f0a14b8b14a041367f2259b3c0e37.zip | |
clkpart -unpart into 'finalize'
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5bc55387b..554c42d68 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -538,16 +538,14 @@ struct SynthXilinxPass : public ScriptPass else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); - run("clean"); - run("clkpart -unpart clkpart"); } else { if (nowidelut) run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); - run("clean"); } + run("clean"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming @@ -564,6 +562,9 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("finalize")) { + if (help_mode || abc9) + run("clkpart -unpart clkpart", "(only if 'abc9')"); + bool do_iopad = iopad || (ise && !noiopad); if (help_mode || !noclkbuf) { if (help_mode || do_iopad) |