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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 10:25:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 10:25:59 -0700 |
| commit | 93fbd56db1c72403881281aa2c3e61bf6e622344 (patch) | |
| tree | 1304abeb9a3dd94101d692a5adf1b735e51d1304 /techlibs/xilinx | |
| parent | bd198aa803bdfc3b21bfa920822805df992e3120 (diff) | |
| download | yosys-93fbd56db1c72403881281aa2c3e61bf6e622344.tar.gz yosys-93fbd56db1c72403881281aa2c3e61bf6e622344.tar.bz2 yosys-93fbd56db1c72403881281aa2c3e61bf6e622344.zip | |
$__ABC_FD_ASYNC_MUX.Q -> Y
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index e4937f646..81696ddb5 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -131,7 +131,7 @@ module \$__ABC_FF_ (input C, D, output Q); endmodule (* abc_box_id = 1000 *) -module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q); +module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Y); // assign Q = S ? B : A; endmodule |