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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:07:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:07:14 -0700 |
| commit | 9398921af1d21b47aa291d240a1f274418adcaf2 (patch) | |
| tree | c93649f494e78cb7745a0f64ce8a04443969cff2 /techlibs/xilinx | |
| parent | 550760cc721e8a617e5ca60b3dda70a223504765 (diff) | |
| download | yosys-9398921af1d21b47aa291d240a1f274418adcaf2.tar.gz yosys-9398921af1d21b47aa291d240a1f274418adcaf2.tar.bz2 yosys-9398921af1d21b47aa291d240a1f274418adcaf2.zip | |
Refactor for one "abc_carry" attribute on module
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5fd9973f4..5a148be01 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -173,8 +173,8 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 3, abc_carry, lib_whitebox *) -module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S); +(* abc_box_id = 3, abc_carry="CI,CO", lib_whitebox *) +module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; assign CO[1] = S[1] ? CO[0] : DI[1]; |