abc9 -keepff -> -dff; refactor dff operations

2 files changed, 58 insertions, 58 deletions

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 1b58c34c0..1d37952f5 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -51,29 +51,29 @@
 //                ||                  ||
 //                ||      /\/\/\/\    ||
 //           D  -->>-----<        >   ||
-//           R  -->>-----<  Comb. >   ||        +----------+
-//          CE  -->>-----<  logic >--->>-- $Q --|$__ABC_FF_|--+-->> Q
-// $abc9_currQ +-->>-----<        >   ||        +----------+  |
-//             |  ||      \/\/\/\/    ||                      |
-//             |  ||                  ||                      |
-//             |  ++==================++                      |
-//             |                                              |
-//             +----------------------------------------------+
+//           R  -->>-----<  Comb. >   ||        +-----------+
+//          CE  -->>-----<  logic >--->>-- $Q --|$__ABC9_FF_|--+-->> Q
+//   abc9_ff.Q +-->>-----<        >   ||        +-----------+  |
+//             |  ||      \/\/\/\/    ||                       |
+//             |  ||                  ||                       |
+//             |  ++==================++                       |
+//             |                                               |
+//             +-----------------------------------------------+
 //
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
 // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
 //     capture asynchronous behaviour
-// (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
+// (c) a special _TECHMAP_REPLACE_.abc9_ff.clock wire to capture its clock
 //     domain and polarity (used when partitioning the module so that `abc9' only
 //     performs sequential synthesis (with reachability analysis) correctly on
 //     one domain at a time) and also used to infer the optional delay target
 //     from the (* abc9_clock_period = %d *) attribute attached to any wire
 //     within
-// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
+// (d) a special _TECHMAP_REPLACE_.abc9_ff.init wire to encode the flop's initial
 //     state
-// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 //
 // In order to perform sequential synthesis, `abc9' also requires that
@@ -108,12 +108,12 @@ module FDRE (output Q, input C, CE, D, R);
     );
   end
   endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -135,12 +135,12 @@ module FDRE_1 (output Q, input C, CE, D, R);
     );
   end
   endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 
 module FDSE (output Q, input C, CE, D, S);
@@ -171,12 +171,12 @@ module FDSE (output Q, input C, CE, D, S);
       .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
     );
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
@@ -197,12 +197,12 @@ module FDSE_1 (output Q, input C, CE, D, S);
       .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
     );
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 
 module FDCE (output Q, input C, CE, D, CLR);
@@ -210,7 +210,7 @@ module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE #(
@@ -227,7 +227,7 @@ module FDCE (output Q, input C, CE, D, CLR);
                                             //     $__ABC9_ASYNC1 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -245,18 +245,18 @@ module FDCE (output Q, input C, CE, D, CLR);
                                            //     $__ABC9_ASYNC0 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE_1 #(
@@ -269,7 +269,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC1 below
     );
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -283,14 +283,14 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC0 below
     );
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 
 module FDPE (output Q, input C, CE, D, PRE);
@@ -298,7 +298,7 @@ module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDCE #(
@@ -314,7 +314,7 @@ module FDPE (output Q, input C, CE, D, PRE);
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC0 below
     );
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -331,18 +331,18 @@ module FDPE (output Q, input C, CE, D, PRE);
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC1 below
     );
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDCE_1 #(
@@ -355,7 +355,7 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC0 below
     );
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -369,14 +369,14 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC1 below
     );
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 `endif
 
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 10aa7be5f..af9f21756 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        flatten design before synthesis\n");
 		log("\n");
 		log("    -dff\n");
-		log("        enable sequential synthesis with 'abc9'\n");
+		log("        run 'abc9' with -dff option\n");
 		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
@@ -559,8 +559,8 @@ struct SynthXilinxPass : public ScriptPass
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
-				if (!dff_mode)
-					abc9_opts += " -keepff";
+				if (dff_mode)
+					abc9_opts += " -dff";
 				run("abc9" + abc9_opts);
 				run("techmap -map +/xilinx/abc9_unmap.v");
 			}