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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-07 15:58:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-07 15:58:55 -0700 |
| commit | 4f0818275fe44c451be59235616061be8ff5e382 (patch) | |
| tree | b960ff2533681caedebeaab53f9b0e87acb2d1ca /techlibs/xilinx | |
| parent | b2e34f932ac37e66435d413ab7a9f0074dc0343f (diff) | |
| download | yosys-4f0818275fe44c451be59235616061be8ff5e382.tar.gz yosys-4f0818275fe44c451be59235616061be8ff5e382.tar.bz2 yosys-4f0818275fe44c451be59235616061be8ff5e382.zip | |
Cleanup
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index ee319a8e3..95546db37 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -25,11 +25,6 @@ // For example, (complex) flip-flops are expected to be described as an // combinatorial box (containing all control logic such as clock enable // or synchronous resets) followed by a basic D-Q flop. - -// ============================================================================ - -// `abc9' requires that complex flops be split into a combinatorial box -// feeding a simple flop ($_ABC9_FF_). // Yosys will automatically analyse the simulation model (described in // cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in // order to extract the combinatorial control logic left behind. @@ -55,8 +50,8 @@ // || || // || /\/\/\/\ || // D -->>-----< > || +------+ -// R -->>-----< Comb. > || |$_ABC_| -// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q +// R -->>-----< Comb. > || |$__ABC| +// CE -->>-----< logic >--->>-- $nextQ --| _FF_ |--+-->> Q // $abc9_currQ +-->>-----< > || +------+ | // | || \/\/\/\/ || | // | || || | |