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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:04:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:04:25 -0700 |
| commit | 3825068a75b2d7ccb0953c92040474f95274b76a (patch) | |
| tree | c42cef274d6d58c0098d019b939850001a70ab5e /techlibs/xilinx | |
| parent | e1ba25d79f0fc623006b250e72093199d0804d52 (diff) | |
| parent | 2f770b7400f6b12ca13e68496977094f92c13680 (diff) | |
| download | yosys-3825068a75b2d7ccb0953c92040474f95274b76a.tar.gz yosys-3825068a75b2d7ccb0953c92040474f95274b76a.tar.bz2 yosys-3825068a75b2d7ccb0953c92040474f95274b76a.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 39c535303..c95ba4969 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -46,12 +46,12 @@ RAM32X1D 4 0 13 2 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Outputs: DPO SPO RAM64X1D 5 0 15 2 -- - - - - - - 124 124 124 124 124 124 - - -124 124 124 124 124 124 - - - - - - 124 - - +- - - - - - - 642 631 472 407 238 127 - - +642 631 472 407 238 127 - - - - - - - - - # SLICEM/A6LUT + F7[AB]MUX # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Outputs: DPO SPO RAM128X1D 6 0 17 2 -- - - - - - - - 314 314 314 314 314 314 292 - - -347 347 347 347 347 347 296 - - - - - - - - - - +- - - - - - - - 1009 998 839 774 605 494 450 - - +1047 1036 877 812 643 532 478 - - - - - - - - - - |