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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-22 08:42:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-22 08:42:34 -0700 |
| commit | 2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (patch) | |
| tree | 02b9412c9249cce3714972c8385d66f8093bfc17 /techlibs/xilinx | |
| parent | 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff) | |
| parent | 408077769ff022f78f10ec1ffb60926361f8dc9f (diff) | |
| download | yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.gz yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.bz2 yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.zip | |
Merge pull request #1 from YosysHQ/master
merge with YosysHQ master
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1bc61daef..590fe61d2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -38,7 +38,7 @@ struct SynthXilinxPass : public Pass { SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -128,7 +128,7 @@ struct SynthXilinxPass : public Pass log(" write_blif <file-name>\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { std::string top_opt = "-auto-top"; std::string edif_file; |