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authorEddie Hung <eddie@fpgeh.com>2019-09-27 12:49:57 -0700
committerMarcin Koƛcielnicki <koriakin@0x04.net>2019-09-30 12:52:43 +0200
commit5b5756b91ee6b514021afbe857135801f3cdcc33 (patch)
tree1a3488f9b0a631e3c906e1095fb3653c323baced /techlibs/xilinx/xc7_cells_xtra.v
parent4535f2c6943107d88e9196c9705fc5d92f604f14 (diff)
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Diffstat (limited to 'techlibs/xilinx/xc7_cells_xtra.v')
-rw-r--r--techlibs/xilinx/xc7_cells_xtra.v30
1 files changed, 0 insertions, 30 deletions
diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v
index 817932e9f..0d16f81c3 100644
--- a/techlibs/xilinx/xc7_cells_xtra.v
+++ b/techlibs/xilinx/xc7_cells_xtra.v
@@ -5149,36 +5149,6 @@ module IDDR_2CLK (...);
input S;
endmodule
-module LDCE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter [0:0] IS_G_INVERTED = 1'b0;
- parameter MSGON = "TRUE";
- parameter XON = "TRUE";
- output Q;
- (* invertible_pin = "IS_CLR_INVERTED" *)
- input CLR;
- input D;
- (* invertible_pin = "IS_G_INVERTED" *)
- input G;
- input GE;
-endmodule
-
-module LDPE (...);
- parameter [0:0] INIT = 1'b1;
- parameter [0:0] IS_G_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- parameter MSGON = "TRUE";
- parameter XON = "TRUE";
- output Q;
- input D;
- (* invertible_pin = "IS_G_INVERTED" *)
- input G;
- input GE;
- (* invertible_pin = "IS_PRE_INVERTED" *)
- input PRE;
-endmodule
-
module ODDR (...);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0;