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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-22 17:36:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-22 17:36:54 +0200 |
| commit | a3a7bb9bf7160d434db7a4737e68f6b015b221ef (patch) | |
| tree | 752e1d94d353e6969cd0c7f324ee3e819e435e2d /techlibs/xilinx/xc6v_cells_xtra.v | |
| parent | 5025aab8c9b47e2a201f7ffd494475882db92398 (diff) | |
| parent | 3b405d985e789ecf0082f724d2d62d3752e4b60c (diff) | |
| download | yosys-a3a7bb9bf7160d434db7a4737e68f6b015b221ef.tar.gz yosys-a3a7bb9bf7160d434db7a4737e68f6b015b221ef.tar.bz2 yosys-a3a7bb9bf7160d434db7a4737e68f6b015b221ef.zip | |
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
Diffstat (limited to 'techlibs/xilinx/xc6v_cells_xtra.v')
0 files changed, 0 insertions, 0 deletions