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author | Marcin KoĆcielnicki <mwk@0x04.net> | 2020-02-04 15:35:47 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-02-07 01:00:29 +0100 |
commit | 30854b9c7f23e2817a445761022668d6b0f7c0ef (patch) | |
tree | 83471ee10f31862015bab189c3684ade82e23c47 /techlibs/xilinx/xc3sa_brams.txt | |
parent | 95c46ccc555769cd9d24bae27e0b7264f06e3d66 (diff) | |
download | yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.gz yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.bz2 yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.zip |
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Diffstat (limited to 'techlibs/xilinx/xc3sa_brams.txt')
-rw-r--r-- | techlibs/xilinx/xc3sa_brams.txt | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc3sa_brams.txt b/techlibs/xilinx/xc3sa_brams.txt new file mode 100644 index 000000000..22a62bd2c --- /dev/null +++ b/techlibs/xilinx/xc3sa_brams.txt @@ -0,0 +1,51 @@ +# Spartan 3A block RAM rules. + +bram $__XILINX_RAMB16 + init 1 + abits 11 @a11d9 + dbits 9 @a11d9 + abits 12 @a12d4 + dbits 4 @a12d4 + abits 13 @a13d2 + dbits 2 @a13d2 + abits 14 @a14d1 + dbits 1 @a14d1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB16BWE + init 1 + abits 9 @a9d36 + dbits 36 @a9d36 + abits 10 @a10d18 + dbits 18 @a10d18 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 4 @a9d36 + enable 1 2 @a10d18 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__XILINX_RAMB16 + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB16BWE + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp +endmatch |