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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-05 17:26:53 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-05 17:26:53 +0200 |
| commit | 95944eb69e45837516ff9c0cba54f77ab89af754 (patch) | |
| tree | 20dabb0609e67176b85461f5d78350506d76eb99 /techlibs/xilinx/tests | |
| parent | 706631225e9ef0d2954c4bef51aaa2817e0f5e86 (diff) | |
| download | yosys-95944eb69e45837516ff9c0cba54f77ab89af754.tar.gz yosys-95944eb69e45837516ff9c0cba54f77ab89af754.tar.bz2 yosys-95944eb69e45837516ff9c0cba54f77ab89af754.zip | |
make all vector-size related integer params in $mem sim model signed
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
Diffstat (limited to 'techlibs/xilinx/tests')
0 files changed, 0 insertions, 0 deletions