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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 16:48:31 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 16:49:48 -0800 |
| commit | d9bf7061cd6a5efc20c053bc96d05650f0fa3a14 (patch) | |
| tree | c24462673a3173cc9887247fea71f1687a2bf316 /techlibs/xilinx/tests/test_dsp_model.v | |
| parent | 42f990f3a6b7928841fa0e290fa2688925485907 (diff) | |
| download | yosys-d9bf7061cd6a5efc20c053bc96d05650f0fa3a14.tar.gz yosys-d9bf7061cd6a5efc20c053bc96d05650f0fa3a14.tar.bz2 yosys-d9bf7061cd6a5efc20c053bc96d05650f0fa3a14.zip | |
Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp_model.v')
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