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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-06 13:03:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-06 13:27:11 +0200 |
| commit | d19866615b5cb1ad24d28df544071dd65f6df78a (patch) | |
| tree | 9b9ea774b64eba1ab8bba1462292d835771c5224 /techlibs/xilinx/tests/bram2.v | |
| parent | 4389d9306ecb64df29115027ad9a948d852448bd (diff) | |
| download | yosys-d19866615b5cb1ad24d28df544071dd65f6df78a.tar.gz yosys-d19866615b5cb1ad24d28df544071dd65f6df78a.tar.bz2 yosys-d19866615b5cb1ad24d28df544071dd65f6df78a.zip | |
Added Xilinx test case for initialized brams
Diffstat (limited to 'techlibs/xilinx/tests/bram2.v')
| -rw-r--r-- | techlibs/xilinx/tests/bram2.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/bram2.v b/techlibs/xilinx/tests/bram2.v new file mode 100644 index 000000000..9444fb172 --- /dev/null +++ b/techlibs/xilinx/tests/bram2.v @@ -0,0 +1,24 @@ +module myram( + input rd_clk, + input [ 7:0] rd_addr, + output reg [15:0] rd_data, + input wr_clk, + input wr_enable, + input [ 7:0] wr_addr, + input [15:0] wr_data +); + reg [15:0] memory [0:255]; + integer i; + + initial begin + for (i = 0; i < 256; i = i+1) + memory[i] = i; + end + + always @(posedge rd_clk) + rd_data <= memory[rd_addr]; + + always @(posedge wr_clk) + if (wr_enable) + memory[wr_addr] <= wr_data; +endmodule |