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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-06 17:07:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-06 17:07:10 +0200 |
| commit | 8520b7fbe0b24dda47749aa870881b6b03480d4a (patch) | |
| tree | bd26ef8c9adc39cb296f04614b3c4fb33714ed13 /techlibs/xilinx/tests/bram2.v | |
| parent | 169d1c471165f77612d049478ca25720071272c4 (diff) | |
| download | yosys-8520b7fbe0b24dda47749aa870881b6b03480d4a.tar.gz yosys-8520b7fbe0b24dda47749aa870881b6b03480d4a.tar.bz2 yosys-8520b7fbe0b24dda47749aa870881b6b03480d4a.zip | |
Added support for initialized xilinx brams
Diffstat (limited to 'techlibs/xilinx/tests/bram2.v')
| -rw-r--r-- | techlibs/xilinx/tests/bram2.v | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/techlibs/xilinx/tests/bram2.v b/techlibs/xilinx/tests/bram2.v index 9444fb172..0a6013ca6 100644 --- a/techlibs/xilinx/tests/bram2.v +++ b/techlibs/xilinx/tests/bram2.v @@ -1,18 +1,29 @@ module myram( input rd_clk, input [ 7:0] rd_addr, - output reg [15:0] rd_data, + output reg [17:0] rd_data, input wr_clk, input wr_enable, input [ 7:0] wr_addr, - input [15:0] wr_data + input [17:0] wr_data ); - reg [15:0] memory [0:255]; + reg [17:0] memory [0:255]; integer i; + function [17:0] hash(input [7:0] k); + reg [31:0] x; + begin + x = {k, ~k, k, ~k}; + x = x ^ (x << 13); + x = x ^ (x >> 17); + x = x ^ (x << 5); + hash = x; + end + endfunction + initial begin for (i = 0; i < 256; i = i+1) - memory[i] = i; + memory[i] = hash(i); end always @(posedge rd_clk) |