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authorwhitequark <whitequark@whitequark.org>2020-06-19 06:15:33 +0000
committerGitHub <noreply@github.com>2020-06-19 06:15:33 +0000
commitede4b10da8fdbdcff900b93c6c723516901483ff (patch)
treed949c995f56d6c07dfe7d18ca46547a3296079b6 /techlibs/xilinx/synth_xilinx.cc
parentbcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff)
parent60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff)
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Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d0de73f83..a0d6c279a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -30,13 +30,13 @@ struct SynthXilinxPass : public ScriptPass
{
SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
- void on_register() YS_OVERRIDE
+ void on_register() override
{
RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
// to one LUT6 (instead of a LUT5 + LUT2)
}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -149,7 +149,7 @@ struct SynthXilinxPass : public ScriptPass
int lut_size;
int widelut_size;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
edif_file.clear();
@@ -176,7 +176,7 @@ struct SynthXilinxPass : public ScriptPass
lut_size = 6;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string run_from, run_to;
clear_flags();
@@ -337,7 +337,7 @@ struct SynthXilinxPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
std::string lut_size_s = std::to_string(lut_size);
if (help_mode)