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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 10:36:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 10:36:27 -0700 |
| commit | e300b1922c13b939231072e83f0ae5c5ff6a558b (patch) | |
| tree | 20c8ffe7a42a4aa2ae9195957e287c875c3a0594 /techlibs/xilinx/synth_xilinx.cc | |
| parent | d342b5b135a85da0df5df0fa2acc25dec5605760 (diff) | |
| parent | 9050b5e1915b05f55c1db279566f34202905f02a (diff) | |
| download | yosys-e300b1922c13b939231072e83f0ae5c5ff6a558b.tar.gz yosys-e300b1922c13b939231072e83f0ae5c5ff6a558b.tar.bz2 yosys-e300b1922c13b939231072e83f0ae5c5ff6a558b.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e84a6714b..1449e792f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -132,6 +132,7 @@ struct SynthXilinxPass : public Pass log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); + log(" clean\n"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); @@ -309,6 +310,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + Pass::call(design, "clean"); } if (check_label(active, run_from, run_to, "check")) |