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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-15 13:50:04 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-15 13:50:04 +0100 |
| commit | b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8 (patch) | |
| tree | 79a58ee5a1f8595b769426faca666c43da9949da /techlibs/xilinx/synth_xilinx.cc | |
| parent | 2e36faeced76fe0a4d19a1febddd070263955034 (diff) | |
| download | yosys-b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8.tar.gz yosys-b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8.tar.bz2 yosys-b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8.zip | |
Added Xilinx MUXF7 and MUXF8 support
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e7308461a..380fdae73 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -75,7 +75,7 @@ struct SynthXilinxPass : public Pass { log(" synth -run fine\n"); log("\n"); log(" map_luts:\n"); - log(" abc -lut 6\n"); + log(" abc -lut 6:8\n"); log(" clean\n"); log("\n"); log(" map_cells:\n"); @@ -147,7 +147,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "abc -lut 6"); + Pass::call(design, "abc -lut 6:8"); Pass::call(design, "clean"); } |