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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 08:58:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 08:58:57 -0700 |
| commit | ae89e6ab26d2d87a604e20ebc14dcda8c9901585 (patch) | |
| tree | a8b9fb4f00eef4abaa1c476e488ded535f372dc6 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 4f44e3399ba6c959c830943c44c4ad728be895fa (diff) | |
| download | yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.tar.gz yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.tar.bz2 yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.zip | |
Add whitebox support to DRAM
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3cee81a7b..ecfb94610 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass { if (check_label("begin")) { if (vpr) - run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); run("read_verilog -lib +/xilinx/cells_xtra.v"); |