diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 16:20:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 16:20:43 -0700 |
| commit | a5f33b5409d9325730204eb776e0046726d55d2c (patch) | |
| tree | bdd66f8874a7fe03f6b68afee2ca4e839665f5b3 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 0364a5d811f79364f35b72935fe90bc188229c19 (diff) | |
| download | yosys-a5f33b5409d9325730204eb776e0046726d55d2c.tar.gz yosys-a5f33b5409d9325730204eb776e0046726d55d2c.tar.bz2 yosys-a5f33b5409d9325730204eb776e0046726d55d2c.zip | |
Move dffinit til after abc
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ee8dec9ee..2676f5915 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -284,8 +284,6 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v"); - Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); } @@ -295,6 +293,8 @@ struct SynthXilinxPass : public Pass Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); } if (check_label(active, run_from, run_to, "check")) |