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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 09:13:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 09:13:39 -0700 |
| commit | 87b8d29a900eef6ec84c87ea7cd87f9a0b744fac (patch) | |
| tree | d1f8dc3d56fddac52be6df691fdec970c46c4717 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 227cc54c162603d4c1a32f7765e81537bf5e2347 (diff) | |
| download | yosys-87b8d29a900eef6ec84c87ea7cd87f9a0b744fac.tar.gz yosys-87b8d29a900eef6ec84c87ea7cd87f9a0b744fac.tar.bz2 yosys-87b8d29a900eef6ec84c87ea7cd87f9a0b744fac.zip | |
Juggle opt calls in synth_xilinx
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 10902a560..0058f626f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -118,7 +118,7 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); - log(" clean\n"); + log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); log(" techmap -map +/techmap.v\n"); @@ -258,11 +258,10 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "opt -fast -full"); + Pass::call(design, "opt -fast"); Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "opt -full"); if (vpr) { Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); @@ -282,6 +281,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { + Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); |