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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:09:34 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:09:34 +0100 |
| commit | 816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (patch) | |
| tree | 9be22cb0d132ebb6f7c361deb61bb7ebf67f1a8a /techlibs/xilinx/synth_xilinx.cc | |
| parent | 6978f3a77baa1220ba0f8a41ca26f5f7bc98dd0a (diff) | |
| download | yosys-816fe6bbe0ad90f7a696dd208dae6db8139dfd00.tar.gz yosys-816fe6bbe0ad90f7a696dd208dae6db8139dfd00.tar.bz2 yosys-816fe6bbe0ad90f7a696dd208dae6db8139dfd00.zip | |
Added Xilinx example for Basys3 board
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b3776b3d8..caa7e205d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -68,6 +68,7 @@ struct SynthXilinxPass : public Pass { log("The following commands are executed by this synthesis command:\n"); log("\n"); log(" begin:\n"); + log(" read_verilog -lib +/xilinx/cells_sim.v\n"); log(" hierarchy -check -top <top>\n"); log("\n"); log(" flatten: (only if -flatten)\n"); @@ -151,6 +152,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "begin")) { + Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str())); } |