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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 07:39:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 07:39:19 -0700 |
| commit | 736e19f02d9980691e244e08b711c5e8c0b4fc76 (patch) | |
| tree | d1b8ad6e3b1f434f895c60aaaeb42af5776527c2 /techlibs/xilinx/synth_xilinx.cc | |
| parent | aa693d5723ef1438d42cd35a26673703b1eff79f (diff) | |
| download | yosys-736e19f02d9980691e244e08b711c5e8c0b4fc76.tar.gz yosys-736e19f02d9980691e244e08b711c5e8c0b4fc76.tar.bz2 yosys-736e19f02d9980691e244e08b711c5e8c0b4fc76.zip | |
t:$dff* -> t:$dff t:$dffe
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 601a6811d..5a3725e7d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -113,7 +113,7 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" simplemap t:$dff* (without -nosrl and without -retime only)\n"); + log(" simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n"); log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); @@ -266,7 +266,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -full"); if (!nosrl && !retime) { - Pass::call(design, "simplemap t:$dff*"); + Pass::call(design, "simplemap t:$dff t:$dffe"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } |