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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:28:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:28:55 -0700 |
| commit | 726e2da8f272a893b355b63c5cc1a18fe0c2f406 (patch) | |
| tree | f118c96a7cf5d80518771e3b7f047fab3cebcdf3 /techlibs/xilinx/synth_xilinx.cc | |
| parent | ae95aba60a573bf34034d6a70931bd55490d3f14 (diff) | |
| parent | a3371e118b05eb9bd5dddb1c20758674ae50a803 (diff) | |
| download | yosys-726e2da8f272a893b355b63c5cc1a18fe0c2f406.tar.gz yosys-726e2da8f272a893b355b63c5cc1a18fe0c2f406.tar.bz2 yosys-726e2da8f272a893b355b63c5cc1a18fe0c2f406.zip | |
Merge branch 'map_cells_before_map_luts' into xc7srl
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f59c0c622..a9e50329c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -121,7 +121,7 @@ struct SynthXilinxPass : public Pass log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); - log(" techmap -map +/techmap.v -map +/xilinx/cells_map.v\n"); + log(" techmap -map +/xilinx/cells_map.v\n"); log(" clean\n"); log("\n"); log(" map_luts:\n"); @@ -296,7 +296,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v"); + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "clean"); } |