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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:18:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:18:36 -0700 |
| commit | 569cd66764f43af9ea73038ce7437ab8557d497e (patch) | |
| tree | 6309ae90b08783f94e87e687f9688f94dc172358 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 9616dbd125171905bccf55fa7fd564e4ae2ca5ab (diff) | |
| parent | d38df68d26f1644539e5116e6b6c360e1c389cc9 (diff) | |
| download | yosys-569cd66764f43af9ea73038ce7437ab8557d497e.tar.gz yosys-569cd66764f43af9ea73038ce7437ab8557d497e.tar.bz2 yosys-569cd66764f43af9ea73038ce7437ab8557d497e.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 796615211..815bf0848 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); + // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply + // Due to current limitations of mul2dsp, we are actually mapping as a 24x17 + // unsigned multiply with MSBs set to 1'b0 + if (!nodsp || help_mode) - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18"); run("alumacc"); run("share"); |