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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-11 08:34:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 5643c1b8c5fbe1a31fcb4027ddbe096e74439cbf (patch) | |
| tree | 73d19c64ea852748b910509e39694c343a0ccaa8 /techlibs/xilinx/synth_xilinx.cc | |
| parent | ab8826ae36890fd01c7897f7800854c01c5bc267 (diff) | |
| download | yosys-5643c1b8c5fbe1a31fcb4027ddbe096e74439cbf.tar.gz yosys-5643c1b8c5fbe1a31fcb4027ddbe096e74439cbf.tar.bz2 yosys-5643c1b8c5fbe1a31fcb4027ddbe096e74439cbf.zip | |
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a6b422b83..4614a2bf9 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -354,7 +354,7 @@ struct SynthXilinxPass : public ScriptPass std::string read_args; if (vpr) read_args += " -D_EXPLICIT_CARRY"; - read_args += " -lib +/xilinx/cells_sim.v"; + read_args += " -lib -specify +/xilinx/cells_sim.v"; run("read_verilog" + read_args); run("read_verilog -lib +/xilinx/cells_xtra.v"); @@ -627,9 +627,7 @@ struct SynthXilinxPass : public ScriptPass else abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str()); if (nowidelut) - abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; - else - abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; + abc9_opts += stringf(" -maxlut %d", lut_size_s); if (dff_mode) abc9_opts += " -dff"; run("abc9" + abc9_opts); |