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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 12:55:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 12:55:52 -0700 |
| commit | 544843da717734ab9bd9bd88f71db2475fc3abc0 (patch) | |
| tree | f069f4b4d6e0acda7b785102dd1e1b6e4179bf64 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 7b7ddbdba79c94266074e516497f4811d2b5bfc7 (diff) | |
| download | yosys-544843da717734ab9bd9bd88f71db2475fc3abc0.tar.gz yosys-544843da717734ab9bd9bd88f71db2475fc3abc0.tar.bz2 yosys-544843da717734ab9bd9bd88f71db2475fc3abc0.zip | |
techmap inside map_cells stage
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 326684daf..cabf0b76e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -283,7 +283,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); |