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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:09:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:09:42 -0700 |
| commit | 4ef26d4755d355e562a173c86d3eace100a266fe (patch) | |
| tree | 6d331a5b3fa83d9072c25f7825cacb4e3d30cea5 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 1c79a32276ef4ae3601cb75e0ab05ba1afe4d385 (diff) | |
| parent | da5f83039527bf50af001671744f351988c3261a (diff) | |
| download | yosys-4ef26d4755d355e562a173c86d3eace100a266fe.tar.gz yosys-4ef26d4755d355e562a173c86d3eace100a266fe.tar.bz2 yosys-4ef26d4755d355e562a173c86d3eace100a266fe.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c72c0ba8c..0a30848aa 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -62,9 +62,6 @@ struct SynthXilinxPass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -nocarry\n"); - log(" disable inference of carry chains\n"); - log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); log("\n"); |