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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-16 12:08:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-16 12:08:03 -0700 |
| commit | 1ec450d6bf34a7aec9b0469b6f295847eb658160 (patch) | |
| tree | d5bb60438cca2906bed1b7d57e02dc3d185c147e /techlibs/xilinx/synth_xilinx.cc | |
| parent | 5f9ba3ea414b6d693cef855e3cd57d61b76a4aeb (diff) | |
| download | yosys-1ec450d6bf34a7aec9b0469b6f295847eb658160.tar.gz yosys-1ec450d6bf34a7aec9b0469b6f295847eb658160.tar.bz2 yosys-1ec450d6bf34a7aec9b0469b6f295847eb658160.zip | |
Try -W 300
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 63ede275f..7b20a7132 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -25,7 +25,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define XC7_WIRE_DELAY "160" +#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate + // to one LUT6 (instead of a LUT5 + LUT2) struct SynthXilinxPass : public ScriptPass { |