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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:18:32 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:18:32 -0700 |
| commit | 32eef26ee277b79736e135a8800625543dd6080a (patch) | |
| tree | 28cd6d5af904ddd2ec2772e2bd1d2378215c1dc7 /techlibs/xilinx/lutrams_map.v | |
| parent | fe58790f3789a79b867660031d7e3e28cb3fff20 (diff) | |
| parent | c499dc3e73390c3bc9bf8045f2e4cad963c1fbad (diff) | |
| download | yosys-32eef26ee277b79736e135a8800625543dd6080a.tar.gz yosys-32eef26ee277b79736e135a8800625543dd6080a.tar.bz2 yosys-32eef26ee277b79736e135a8800625543dd6080a.zip | |
Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
Diffstat (limited to 'techlibs/xilinx/lutrams_map.v')
| -rw-r--r-- | techlibs/xilinx/lutrams_map.v | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v new file mode 100644 index 000000000..77041ca86 --- /dev/null +++ b/techlibs/xilinx/lutrams_map.v @@ -0,0 +1,97 @@ + +module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [31:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR; + output A1DATA; + + input [4:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM32X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPRA4(A1ADDR[4]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .A4(B1ADDR[4]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 64'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [5:0] A1ADDR; + output A1DATA; + + input [5:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM64X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPRA4(A1ADDR[4]), + .DPRA5(A1ADDR[5]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .A4(B1ADDR[4]), + .A5(B1ADDR[5]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [127:0] INIT = 128'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [6:0] A1ADDR; + output A1DATA; + + input [6:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM128X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA(A1ADDR), + .DPO(A1DATA), + + .A(B1ADDR), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + |