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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:21 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:21 -0800 |
| commit | a73f96594f4688afc85098b485ef7788e79f5c33 (patch) | |
| tree | 8b4fdf160bcb8a8db62a309fd409096a721bb3c7 /techlibs/xilinx/lutrams.txt | |
| parent | 9935370ada858da56b5d61a3806768af11565a47 (diff) | |
| parent | 5d009964266e3b52a01c72ee930601d0ebf3a838 (diff) | |
| download | yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.gz yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.bz2 yosys-a73f96594f4688afc85098b485ef7788e79f5c33.zip | |
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
Diffstat (limited to 'techlibs/xilinx/lutrams.txt')
| -rw-r--r-- | techlibs/xilinx/lutrams.txt | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 2613c206c..29f6b05cc 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM16X1D + init 1 + abits 4 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM32X1D init 1 abits 5 @@ -38,6 +51,70 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram + +bram $__XILINX_RAM32X6SDP + init 1 + abits 5 + dbits 6 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X3SDP + init 1 + abits 6 + dbits 3 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM32X2Q + init 1 + abits 5 + dbits 2 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X1Q + init 1 + abits 6 + dbits 1 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +# Disabled for now, pending support for LUT4 arches +# since on LUT6 arches this occupies same area as +# a RAM32X1D +#match $__XILINX_RAM16X1D +# min bits 2 +# min wports 1 +# make_outreg +# or_next_if_better +#endmatch + match $__XILINX_RAM32X1D min bits 3 min wports 1 @@ -56,5 +133,35 @@ match $__XILINX_RAM128X1D min bits 9 min wports 1 make_outreg + or_next_if_better +endmatch + + +match $__XILINX_RAM32X6SDP + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X3SDP + min bits 6 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM32X2Q + min bits 5 + min rports 3 + min wports 1 + make_outreg + or_next_if_better endmatch +match $__XILINX_RAM64X1Q + min bits 5 + min rports 3 + min wports 1 + make_outreg +endmatch |