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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:08:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:08:56 -0700 |
| commit | 295bb23ae06d36acc8ced4825ece6003470cd357 (patch) | |
| tree | 64492ad6f7873d32b72a5a6e80ef85bfc2e3610c /techlibs/xilinx/ff_map.v | |
| parent | da487c4f31fd2d97c0d7110010e7379e5445ceb0 (diff) | |
| download | yosys-295bb23ae06d36acc8ced4825ece6003470cd357.tar.gz yosys-295bb23ae06d36acc8ced4825ece6003470cd357.tar.bz2 yosys-295bb23ae06d36acc8ced4825ece6003470cd357.zip | |
Wrap FDRE with $__ABC_FDRE containing comb
Diffstat (limited to 'techlibs/xilinx/ff_map.v')
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index 13beaa6ae..ba34425d6 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -23,7 +23,15 @@ `ifndef _NO_FFS module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule -module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule +module \$_DFF_P_ (input D, C, output Q); +`ifndef _ABC + FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); +`else + wire Q_next; + \$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0)); + \$_DFF_P_ abc_dff (.D(Q_next), .Q(Q), .C(C)); +`endif +endmodule module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule |