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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-16 10:42:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-16 10:42:00 -0700 |
| commit | 0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37 (patch) | |
| tree | be0fd326e57bb5bb5e9b559f4573c220fdb03078 /techlibs/xilinx/ff_map.v | |
| parent | 59dcfcc9193160302e1f8ca2e95b473241b1752a (diff) | |
| download | yosys-0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37.tar.gz yosys-0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37.tar.bz2 yosys-0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37.zip | |
Cleanup
Diffstat (limited to 'techlibs/xilinx/ff_map.v')
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index bd36c78fc..5ad73aa63 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -27,9 +27,9 @@ module \$_DFF_P_ (input D, C, output Q); `ifndef _ABC FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); `else - wire Q_next; - \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0)); - \$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q)); + wire \$nextQ ; + \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(1'b1), .R(1'b0)); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); `endif endmodule @@ -38,9 +38,9 @@ module \$_DFFE_PP_ (input D, C, E, output Q); `ifndef _ABC FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); `else - wire Q_next; - \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(E), .R(1'b0)); - \$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q)); + wire \$nextQ ; + \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(E), .R(1'b0)); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); `endif endmodule |