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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-27 09:30:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-27 09:30:17 +0100 |
| commit | 90b016716b363977cf3dfc84d9502913469296ec (patch) | |
| tree | 0b0d669bc38f4e865600c31496117a19a6ca5e9c /techlibs/xilinx/example_sim_counter/counter_tb.v | |
| parent | 02f321b6fcd17c94ad633d1070c03cbec1eb86e8 (diff) | |
| download | yosys-90b016716b363977cf3dfc84d9502913469296ec.tar.gz yosys-90b016716b363977cf3dfc84d9502913469296ec.tar.bz2 yosys-90b016716b363977cf3dfc84d9502913469296ec.zip | |
Moved simple xilinx counter sim example to subdir
Diffstat (limited to 'techlibs/xilinx/example_sim_counter/counter_tb.v')
| -rw-r--r-- | techlibs/xilinx/example_sim_counter/counter_tb.v | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/techlibs/xilinx/example_sim_counter/counter_tb.v b/techlibs/xilinx/example_sim_counter/counter_tb.v new file mode 100644 index 000000000..b6b64269e --- /dev/null +++ b/techlibs/xilinx/example_sim_counter/counter_tb.v @@ -0,0 +1,61 @@ +`timescale 1 ns / 1 ps + +module testbench; + +reg clk, en, rst; +wire [3:0] count; + +counter uut_counter( + .clk(clk), + .count(count), + .en(en), + .rst(rst) +); + +initial begin + clk <= 0; + forever begin + #50; + clk <= ~clk; + end +end + +initial begin + @(posedge clk); + forever begin + @(posedge clk); + $display("%d", count); + end +end + +initial begin + rst <= 1; en <= 0; @(posedge clk); + rst <= 1; en <= 0; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 1; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 1; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + $finish; +end + +endmodule |