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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
| commit | 3cbfa3815ee0c40fcafe80d56afec97c36368f06 (patch) | |
| tree | 4f1ccade1714d31d8bb1443b4a1735a3174f0492 /techlibs/xilinx/example_sim_counter/counter.v | |
| parent | 816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (diff) | |
| download | yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.tar.gz yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.tar.bz2 yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.zip | |
Removed old XST-based xilinx examples
Diffstat (limited to 'techlibs/xilinx/example_sim_counter/counter.v')
| -rw-r--r-- | techlibs/xilinx/example_sim_counter/counter.v | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/techlibs/xilinx/example_sim_counter/counter.v b/techlibs/xilinx/example_sim_counter/counter.v deleted file mode 100644 index 72208bd80..000000000 --- a/techlibs/xilinx/example_sim_counter/counter.v +++ /dev/null @@ -1,12 +0,0 @@ -module counter (clk, rst, en, count); - - input clk, rst, en; - output reg [3:0] count; - - always @(posedge clk) - if (rst) - count <= 4'd0; - else if (en) - count <= count + 4'd1; - -endmodule |