diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 14:20:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 14:20:43 -0700 |
| commit | b97fe6e86651b3a4736c46a49d76878beb088a8c (patch) | |
| tree | 14178cb797e6c9a3d7c46ded4d633c11407da9a9 /techlibs/xilinx/drams_map.v | |
| parent | 9cb0456b6f9fa86240a747bab9780a28001b1a02 (diff) | |
| download | yosys-b97fe6e86651b3a4736c46a49d76878beb088a8c.tar.gz yosys-b97fe6e86651b3a4736c46a49d76878beb088a8c.tar.bz2 yosys-b97fe6e86651b3a4736c46a49d76878beb088a8c.zip | |
Work in progress for renaming labels/options in synth_xilinx
Diffstat (limited to 'techlibs/xilinx/drams_map.v')
| -rw-r--r-- | techlibs/xilinx/drams_map.v | 97 |
1 files changed, 0 insertions, 97 deletions
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v deleted file mode 100644 index 77041ca86..000000000 --- a/techlibs/xilinx/drams_map.v +++ /dev/null @@ -1,97 +0,0 @@ - -module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); - parameter [31:0] INIT = 32'bx; - parameter CLKPOL2 = 1; - input CLK1; - - input [4:0] A1ADDR; - output A1DATA; - - input [4:0] B1ADDR; - input B1DATA; - input B1EN; - - RAM32X1D #( - .INIT(INIT), - .IS_WCLK_INVERTED(!CLKPOL2) - ) _TECHMAP_REPLACE_ ( - .DPRA0(A1ADDR[0]), - .DPRA1(A1ADDR[1]), - .DPRA2(A1ADDR[2]), - .DPRA3(A1ADDR[3]), - .DPRA4(A1ADDR[4]), - .DPO(A1DATA), - - .A0(B1ADDR[0]), - .A1(B1ADDR[1]), - .A2(B1ADDR[2]), - .A3(B1ADDR[3]), - .A4(B1ADDR[4]), - .D(B1DATA), - .WCLK(CLK1), - .WE(B1EN) - ); -endmodule - -module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); - parameter [63:0] INIT = 64'bx; - parameter CLKPOL2 = 1; - input CLK1; - - input [5:0] A1ADDR; - output A1DATA; - - input [5:0] B1ADDR; - input B1DATA; - input B1EN; - - RAM64X1D #( - .INIT(INIT), - .IS_WCLK_INVERTED(!CLKPOL2) - ) _TECHMAP_REPLACE_ ( - .DPRA0(A1ADDR[0]), - .DPRA1(A1ADDR[1]), - .DPRA2(A1ADDR[2]), - .DPRA3(A1ADDR[3]), - .DPRA4(A1ADDR[4]), - .DPRA5(A1ADDR[5]), - .DPO(A1DATA), - - .A0(B1ADDR[0]), - .A1(B1ADDR[1]), - .A2(B1ADDR[2]), - .A3(B1ADDR[3]), - .A4(B1ADDR[4]), - .A5(B1ADDR[5]), - .D(B1DATA), - .WCLK(CLK1), - .WE(B1EN) - ); -endmodule - -module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); - parameter [127:0] INIT = 128'bx; - parameter CLKPOL2 = 1; - input CLK1; - - input [6:0] A1ADDR; - output A1DATA; - - input [6:0] B1ADDR; - input B1DATA; - input B1EN; - - RAM128X1D #( - .INIT(INIT), - .IS_WCLK_INVERTED(!CLKPOL2) - ) _TECHMAP_REPLACE_ ( - .DPRA(A1ADDR), - .DPO(A1DATA), - - .A(B1ADDR), - .D(B1DATA), - .WCLK(CLK1), - .WE(B1EN) - ); -endmodule - |