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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 08:22:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-25 08:22:57 -0700 |
| commit | 58629dc2ce5ebd24bf37ab429c2723db75a772de (patch) | |
| tree | 0d1c69537e92418e897051df18a05632ba5ce3fc /techlibs/xilinx/drams_map.v | |
| parent | e754bce047df931cef441d7ff50cb5ec13136ac3 (diff) | |
| parent | efd04880dbeb2021c503c82ad962fe8c5d6802d4 (diff) | |
| download | yosys-58629dc2ce5ebd24bf37ab429c2723db75a772de.tar.gz yosys-58629dc2ce5ebd24bf37ab429c2723db75a772de.tar.bz2 yosys-58629dc2ce5ebd24bf37ab429c2723db75a772de.zip | |
Merge pull request #1129 from YosysHQ/eddie/ram32x1d
Add RAM32X1D support
Diffstat (limited to 'techlibs/xilinx/drams_map.v')
| -rw-r--r-- | techlibs/xilinx/drams_map.v | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v index 47476b592..77041ca86 100644 --- a/techlibs/xilinx/drams_map.v +++ b/techlibs/xilinx/drams_map.v @@ -1,4 +1,38 @@ +module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [31:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR; + output A1DATA; + + input [4:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM32X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPRA4(A1ADDR[4]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .A4(B1ADDR[4]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; |