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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-24 10:20:46 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-24 10:20:46 -0700 |
| commit | c66b7402c06455535bb43ee65fe20515b5b9c0ee (patch) | |
| tree | ad135d83bf75e72b65e3136b4f6746c1f9cafab3 /techlibs/xilinx/drams.txt | |
| parent | 349c47250a9779bc58634870d2e3facfe95fbff8 (diff) | |
| parent | a66f17b6a78af8f6989235f0c72d5548b0560a58 (diff) | |
| download | yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.tar.gz yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.tar.bz2 yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs/xilinx/drams.txt')
| -rw-r--r-- | techlibs/xilinx/drams.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt index 91632bcee..2613c206c 100644 --- a/techlibs/xilinx/drams.txt +++ b/techlibs/xilinx/drams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM64X1D init 1 abits 6 @@ -25,6 +38,13 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM64X1D min bits 5 min wports 1 |