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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 12:29:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 12:29:35 -0700 |
| commit | 8684b58bed2875ab67e9b12912d791f9d588f272 (patch) | |
| tree | e66d456aec1ffe83827ac7cb589bdbf1275cf67e /techlibs/xilinx/cells_xtra.py | |
| parent | f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf (diff) | |
| parent | a274b7cc86d4f64541d3d2903b4eeed4616ab1d8 (diff) | |
| download | yosys-8684b58bed2875ab67e9b12912d791f9d588f272.tar.gz yosys-8684b58bed2875ab67e9b12912d791f9d588f272.tar.bz2 yosys-8684b58bed2875ab67e9b12912d791f9d588f272.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 561a61943..13dbc0e14 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -108,8 +108,8 @@ XC6S_CELLS = [ # Cell('FDRE'), # Cell('FDSE'), Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), # Slice/CLB primitives. |