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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-03-21 08:53:22 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-03-23 09:44:36 +0100 |
| commit | f35bdaa5278b408e94ac8c97a06c3f7f0fe1773a (patch) | |
| tree | 8089e498e0669ce6d0d9338644fe6d5bc4b4424e /techlibs/xilinx/cells_sim.v | |
| parent | 23826e5152483c39a617ee1c696c3b48a0c2b756 (diff) | |
| download | yosys-f35bdaa5278b408e94ac8c97a06c3f7f0fe1773a.tar.gz yosys-f35bdaa5278b408e94ac8c97a06c3f7f0fe1773a.tar.bz2 yosys-f35bdaa5278b408e94ac8c97a06c3f7f0fe1773a.zip | |
Update Xilinx cell definitions, fixes #3699
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index e6e15b16e..8b0c913aa 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -33,8 +33,12 @@ module IBUF( output O, (* iopad_external_pin *) input I); - parameter IOSTANDARD = "default"; - parameter IBUF_LOW_PWR = 0; + parameter CCIO_EN = "TRUE"; + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; assign O = I; specify (I => O) = 0; @@ -56,7 +60,8 @@ module OBUF( (* iopad_external_pin *) output O, input I); - parameter IOSTANDARD = "default"; + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; parameter DRIVE = 12; parameter SLEW = "SLOW"; assign O = I; |