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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 12:01:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | a6fec9fe6052d2ec74fec4417be2fec45dea0df0 (patch) | |
| tree | 92c3dda81a0d5946ce1f316da7a46afe1a871aa1 /techlibs/xilinx/cells_sim.v | |
| parent | 3ea5506f812879c0ecf66431efde002493e11bdf (diff) | |
| download | yosys-a6fec9fe6052d2ec74fec4417be2fec45dea0df0.tar.gz yosys-a6fec9fe6052d2ec74fec4417be2fec45dea0df0.tar.bz2 yosys-a6fec9fe6052d2ec74fec4417be2fec45dea0df0.zip | |
abc9_ops: use TimingInfo for -prep_{lut,box} too
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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