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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:00 -0800 |
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| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:00 -0800 |
| commit | 8aab7fe7e64b1c213d924126e30994ab7b6d4625 (patch) | |
| tree | fb1d094769e8a56d4babdb03550cb88d6f332405 /techlibs/xilinx/cells_sim.v | |
| parent | fe4d6898de378260c659dca08398fa434d71f7f0 (diff) | |
| download | yosys-8aab7fe7e64b1c213d924126e30994ab7b6d4625.tar.gz yosys-8aab7fe7e64b1c213d924126e30994ab7b6d4625.tar.bz2 yosys-8aab7fe7e64b1c213d924126e30994ab7b6d4625.zip | |
Fix SRL16/32 techmap off-by-one
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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