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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-10-01 11:04:32 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-01 11:04:32 +0300 |
| commit | e092c4ae6b60cf67efd16efbfbf739895ad501c0 (patch) | |
| tree | 939a5b94d14a11df511aa95482458b33a1f6139f /techlibs/xilinx/cells_map.v | |
| parent | 1070f2e90b9ba37856932189ef09a0f2316d9a21 (diff) | |
| parent | d963e8c2c6207ad98d48dc528922ad58c030173f (diff) | |
| download | yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.gz yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.bz2 yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.zip | |
Merge branch 'master' into SergeyDegtyar/efinix
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index b8e5bafc7..a15884ec4 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -331,7 +331,6 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y) endmodule `endif -`ifndef _ABC module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); output O; input I0, I1, I2, I3, S0, S1; @@ -364,4 +363,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); else MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule -`endif |