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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-06 15:41:13 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-06 15:41:13 +0200 |
| commit | d187be39d608966f53d6c2ba4d45de94a584d476 (patch) | |
| tree | 30b9820eddba4341c7270d5b255758967ed7eaf0 /techlibs/xilinx/cells_map.v | |
| parent | 5c2c0b4bb2ade51396da3acbcce0d5916fb1c7d6 (diff) | |
| parent | 20268d12a51e157effc209de5613f0ac8308a61f (diff) | |
| download | yosys-d187be39d608966f53d6c2ba4d45de94a584d476.tar.gz yosys-d187be39d608966f53d6c2ba4d45de94a584d476.tar.bz2 yosys-d187be39d608966f53d6c2ba4d45de94a584d476.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 704ab21b1..40789ddbe 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -17,6 +17,16 @@ * */ +// Convert negative-polarity reset to positive-polarity +(* techmap_celltype = "$_DFF_NN0_" *) +module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$_DFF_PN0_" *) +module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$_DFF_NN1_" *) +module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$_DFF_PN1_" *) +module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule + module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; |