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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-04 12:32:30 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-05-04 12:32:30 +0200 |
| commit | 47eb150eec1530384c586971bcf8ec270e1d6acc (patch) | |
| tree | 54032b632244a88fd6f2e7b84cfa7ced958b23a1 /techlibs/xilinx/cells_map.v | |
| parent | a572b495387743a58111e7264917a497faa17ebf (diff) | |
| parent | d6bdefd2e93ad25fd63103d4b76a5573debc6d03 (diff) | |
| download | yosys-47eb150eec1530384c586971bcf8ec270e1d6acc.tar.gz yosys-47eb150eec1530384c586971bcf8ec270e1d6acc.tar.bz2 yosys-47eb150eec1530384c586971bcf8ec270e1d6acc.zip | |
Merge pull request #537 from mithro/yosys-vpr
Improving Yosys when used with VPR
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 8e5a83ce5..0771be0b9 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -15,6 +15,7 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED( module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule +`ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -82,3 +83,4 @@ module \$lut (A, Y); end endgenerate endmodule +`endif |