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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-24 10:20:46 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-24 10:20:46 -0700 |
| commit | c66b7402c06455535bb43ee65fe20515b5b9c0ee (patch) | |
| tree | ad135d83bf75e72b65e3136b4f6746c1f9cafab3 /techlibs/xilinx/arith_map.v | |
| parent | 349c47250a9779bc58634870d2e3facfe95fbff8 (diff) | |
| parent | a66f17b6a78af8f6989235f0c72d5548b0560a58 (diff) | |
| download | yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.tar.gz yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.tar.bz2 yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs/xilinx/arith_map.v')
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 09a5f07e8..5c848d4e6 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -180,7 +180,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part + CARRY4 carry4_1st_part ( .CYINIT(CI), .CI (1'd0), @@ -207,7 +207,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full + CARRY4 carry4_1st_full ( .CYINIT(CI), .CI (1'd0), |