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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:52:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:52:46 -0700 |
| commit | 513c962a71b7ff08c037e8590d26b9b09603dfb4 (patch) | |
| tree | c46b5e6f6f0f94a55f6601193f98b3ca9d83ff50 /techlibs/xilinx/arith_map.v | |
| parent | f7a9769c140f6a56e51d7384dfd8e76bf2aef66d (diff) | |
| parent | 1e838a8913afa36a57d425f26ea881f5071b8b5d (diff) | |
| download | yosys-513c962a71b7ff08c037e8590d26b9b09603dfb4.tar.gz yosys-513c962a71b7ff08c037e8590d26b9b09603dfb4.tar.bz2 yosys-513c962a71b7ff08c037e8590d26b9b09603dfb4.zip | |
Merge remote-tracking branch 'origin/xc7mux' into xaig
Diffstat (limited to 'techlibs/xilinx/arith_map.v')
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 09a5f07e8..5c848d4e6 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -180,7 +180,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part + CARRY4 carry4_1st_part ( .CYINIT(CI), .CI (1'd0), @@ -207,7 +207,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full + CARRY4 carry4_1st_full ( .CYINIT(CI), .CI (1'd0), |